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74F251A 8-Input Multiplexer with 3-STATE Outputs
April 1988 Revised September 2000
74F251A 8-Input Multiplexer with 3-STATE Outputs
General Description
The 74F251A is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided.
Features
s Multifunctional capability s On-chip select logic decoding s Inverting and non-inverting 3-STATE outputs
Ordering Code:
Order Number 74F251ASC 74F251ASJ 74F251APC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 2000 Fairchild Semiconductor Corporation
DS009504
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74F251A
Unit Loading/Fan Out
Pin Names S0-S2 OE I0-I7 Z Z Select Inputs 3-STATE Output Enable Input (Active LOW) Multiplexer Inputs 3-STATE Multiplexer Output Complementary 3-STATE Multiplexer Output Description U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3) 150/40 (33.3) Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA
-3 mA/24 mA (20 mA) -3 mA/24 mA (20 mA)
Functional Description
This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is: Z = OE *(I0*S0*S1 *S2 + I1*S0*S 1*S2 + I2*S0*S1*S2 + I3*S0*S1*S2 + I4*S0*S1*S2 + I5*S0*S1*S2 + I6*S0*S1*S2 + I7*S0*S1*S2) When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltages.
Truth Table
Inputs OE H L L L L L L L L S2 X L L L L H H H H S1 X L L H H L L H H S0 X L H L H L H L H Outputs Z Z I0 I1 I2 I3 I4 I5 I6 I7 Z Z I0 I1 I2 I3 I4 I5 I6 I7
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F251A
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCL ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current 15 16 -60 4.75 3.75 -0.6 50 -50 -150 500 22 24 10% VCC 2.5 2.4 2.7 2.7 0.5 5.0 7.0 50 V A A A V A mA A A mA A mA mA Min Max Max Max 0.0 0.0 Max Max Max Max 0.0V Max Max V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -1 mA IOH = -3 mA IOL = 24 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V VO = LOW VO = HIGH Z
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74F251A
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay Sn to Z Propagation Delay Sn to Z Propagation Delay In to Z Propagation Delay In to Z Output Enable Time OE to Z Output Disable Time OE to Z Output Enable Time OE to Z Output Disable Time OE to Z 3.5 3.2 4.5 4.0 3.0 1.5 3.5 3.5 2.5 2.5 2.5 1.5 3.5 3.5 2.0 1.5 VCC = +5.0V CL = 50 pF Typ 6.0 5.0 7.5 6.0 5.0 2.5 5.0 5.5 4.3 4.3 4.0 3.0 5.0 5.5 3.8 3.0 Max 9.0 7.5 10.5 8.5 6.5 4.0 7.0 7.0 6.0 6.0 5.5 4.5 7.0 7.5 5.5 4.5 TA = -55C to +125C VCC = 5.0V CL = 50 pF Min 3.5 3.2 3.5 3.0 2.5 1.5 2.5 3.5 2.0 2.5 2.5 1.5 3.0 3.5 2.0 1.5 Max 11.5 8.0 14.0 10.5 8.0 6.0 9.0 9.0 7.0 7.5 6.0 5.0 8.5 9.0 5.5 5.5 TA = 0C to +70C VCC = 5.0V CL = 50 pF Min 3.5 3.2 4.5 4.0 3.0 1.5 2.5 3.5 2.5 2.5 2.5 1.5 3.0 3.5 2.0 1.5 Max 9.5 7.5 12.5 9.0 7.0 5.0 8.0 7.5 7.0 6.5 6.0 4.5 7.5 8.0 5.5 4.5 ns ns ns ns ns ns Units
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74F251A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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74F251A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74F251A 8-Input Multiplexer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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